ModelSim / Questa Core: HDL Simulation
ModelSim /Questa Core: HDL Simulation teaches users new to using ModelSim or Questa SIM for HDL simulation.
You will learn how to effectively use ModelSim/Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs.
CONTENT I GOALS
Support of HDL behavioral simulations
Basic concepts in the digital design flow
Introduction on how to invoke the Visualizer debug environment
Hands-on lab exercises
Requirements: Some VHDL or Verilog knowledge I Some familiarity with digital design concept I Duration: 1 day I Language: English / optional German I Price: upon request
More information
Dates
upon request
We are happy to offer further options such as live online sessions and on-site training upon request.
Nuestra sede
Cadlog S.L.
C/Bahía de Pollensa, nº5
28042 - Madrid (España)
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