UVM Testbench Made Easy
Due to the complexity of the UVM library, creating a testbench is a time consuming task and requires extensive knowledge of the capabilities offered by the library. To support verification engineers in the initial creation of a testbench infrastructure, the UVM framework was developed to create a UVM testbench very quickly. This can be simulated immediately and is adapted to the use case by making changes in some places using application specific code.
After a short introduction to some UVM classes and expressions, the workshop UVM TESTBENCH EASY quickly turns to the details of the UVM framework.
The course is aimed at verification engineers with no prior UVM knowledge who want to get started using UVM testbenches.
The goal of the course is to create a complete UVM testbench using the Siemens EDA UVM Framework (UVMF), which is then supplemented with application specific code in a few places.
CONTENT I GOALS
Introduction
UVM Basics | UVM Framework | UVMF Base Classes
Introducing UVMF API
Practical Example: Creation of a UVM Testbench
Conclusion
Requirements: Knowledge of SystemVerilog and OOP concepts I Duration: 2 days I Language: English / optional German I Price: 1.400 Euro
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Dates
Upon request
We are happy to offer further options such as live online sessions and on-site training upon request.
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